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Srinath R. Naidu obtained his B.Tech degree from the Institute of Technology, BHU in 1996. After completing his master's degree from the Indian Institute of Science, Bangalore in 1998 he went on to finish his Ph.D in the area of statistical timing analysis for digital integrated circuits from Eindhoven University of Technology in 2004. After completing his Ph.D he worked for Magma Design Automation Inc in the area of statistical timing analysis. His last work assignment before joining IIIT was with Cadence Design Systems in the area of low power synthesis.His research interests are mainly in the area of electronic design automation including statistical timing analysis and optimisation for digital circuits, power analysis and optimization and formal verification. He is also interested in combinatorial optimization, and design and analysis of algorithms.

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